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  • Formally Verifying a Microprocessor Using a Simulation Methodology
  • Abstract Formal verification is becoming a useful means of validating designs. We have developed a methodology for formally verifying dataintensive circuits (e.g., processors) with sophisticated timi...
  • Rating:   1 Star      Views: (2004)     Pages: (0)     Uploaded: Publication Date: 6-10 June 1994
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  • Using SAT for combinational equivalence checking
  • Abstract This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems. A number of re...
  • Rating:   1 Star      Views: (2004)     Pages: (0)     Uploaded: Publication Date: 2001
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  • An integrated environment for HDL verification
  • Abstract The functional verification of a digital design is an expensive step in the design process. As designs become more complex, simulation is challenged throughout the design and verification pr...
  • Rating:   1 Star      Views: (2008)     Pages: (0)     Uploaded: Publication Date: 27-29 Mar 1995
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  • Simulation approaches for strongly coupled interconnect systems
  • Abstract Shrinking feature sizes and increasing speeds of operation make interconnect-related effects very relevant for current circuit verification methodologies. Reliable and accurate system verifi...
  • Rating:   1 Star      Views: (2003)     Pages: (0)     Uploaded: Publication Date: 2001
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