Group - Bill Gates (frontiersman)


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"Swiftwater" Bill Gates was an American frontiersman and fortune hunter, and a fixture in stories of the Klondike Gold Rush. He made and lost several fortunes, and died in Seattle in 1935. 



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  • "Swiftwater" Bill Gates was an American frontiersman and fortune hunter, and a fixture in stories of the Klondike Gold Rush. He made and lost several fortunes, and died in Seattle in 1935.

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     Related Documents
  • The Long Arc Behind Bill Gates' Wealth, Part 2

  • Abstract: Abstract Did Bill Gates acquire most of his wealth by fair means or foul? Last issue's column examined the 1980s and early 1990s and largely saw fair actions. A few fell on the border. Today we ask about the mid-1990s and beyond. What a period this was for Gates. The diffusion of the Internet required a redirection of numerous Microsoft activities. Gates had the skills to lead such an organizational renewal, and he did. Those actions were impressive. The Internet also raised numerous challenges to Microsoft's market dominance. In protecting that dominance, Gates was accused of committing many...

  • The Long Arc Behind Bill Gates' Wealth, Part 2

  • Abstract: Abstract Did Bill Gates acquire most of his wealth by fair means or foul? Last issue's column examined the 1980s and early 1990s and largely saw fair actions. A few fell on the border. Today we ask about the mid-1990s and beyond. What a period this was for Gates. The diffusion of the Internet required a redirection of numerous Microsoft activities. Gates had the skills to lead such an organizational renewal, and he did. Those actions were impressive. The Internet also raised numerous challenges to Microsoft's market dominance. In protecting that dominance, Gates was accused of committing many...

  • Split gates: A low swing technique for reducing power for high fanout ...

  • Abstract: Abstract We consider the problem of reducing power for heavily loaded intra-module interconnect. Such lines are dominated by a heavy capacitive load with line resistance being smaller than the driver resistance. A method - split gates - of modifying the standard CMOS inverter is provided by splitting the inverter into a driver and receiver circuitry. The scheme allows a reduction in active power by limiting the voltage swing on the interconnect and a reduction in standby power by leveraging the presence of stacked devices. It is a low overhead method which does not require the use of multiple...

  • Behavioral model of V and V+ gates to implement the reversible circuit...

  • Abstract: Abstract This paper addresses using quantum gates to implement binary reversible logic circuits. We propose behavioral models for well known V and V+ quantum gates. Our proposed representation is used to synthesize reversible logic circuits instead of using the known unitary matrix form of quantum gates. This technique allows V and V+ gates to be represented in truth table forms. Results show that our technique can be used to synthesize circuits with bigger sizes and gate counts in compare with unitary matrix form of these gates. Several reversible circuit benchmarks are optimized and compare...

  • Majority gates vs general weighted threshold gates 1992 75 citations ?...

  • Abstract: Abstract. In this paper we study small depth circuits that contain threshold gates (with or without weights) and parity gates. All circuits we consider are of polynomial size. We prove several results which complete the work on characterizing possible inclusions between many classes defined by small depth circuits. These results are the following: 1. A single threshold gate with weights cannot in general be replaced by a polynomial fan-in unweighted threshold gate of parity gates. 2. On the other hand it can be replaced by a depth 2 unweighted threshold circuit of polynomial size. An extension...

  • Behavioral model of V and V+ gates to implement the reversible circuit...

  • Abstract: Abstract This paper addresses using quantum gates to implement binary reversible logic circuits. We propose behavioral models for well known V and V+ quantum gates. Our proposed representation is used to synthesize reversible logic circuits instead of using the known unitary matrix form of quantum gates. This technique allows V and V+ gates to be represented in truth table forms. Results show that our technique can be used to synthesize circuits with bigger sizes and gate counts in compare with unitary matrix form of these gates. Several reversible circuit benchmarks are optimized and compare...

  • Majority Gates vs General Weighted Threshold Gates 1992 70 citations ?...

  • Abstract: . In this paper we study small depth circuits that contain threshold gates (with or without weights) and parity gates. All circuits we consider are of polynomial size. We prove several results which complete the work on characterizing possible inclusions between many classes defined by small depth circuits. These results are the following: 1. A single threshold gate with weights cannot in general be replaced by a polynomial fan-in unweighted threshold gate of parity gates. 2. On the other hand it can be replaced by a depth 2 unweighted threshold circuit of polynomial size. An extension of this...

  • High-speed low-power logic gates using floating gates

  • Abstract: Abstract Low power consumption is attractive because of portability and reliability considerations. One way to reduce this power consumption is lowering the supply voltage. However, low supply voltages leads to reduced time performance if the transistor threshold voltage is not scaled accordingly. To solve this, technologies with reduced threshold voltage devices have emerged. Instead, in this paper we resort to a circuit technique based on floating gate devices in order to lower the threshold voltage. It allows fast operation of logic gates at a low supply voltage in standard technologies. T...

  • Reliability of Power Gaas FET's-Au Gates and Al-Au Linked Gates

  • Abstract: Abstract An investigation of the reliability of two types of commercial microwave power GaAs FET's has been carried out. Mean-time-to-failure data for a device mounted face-up with Al gates but without an Al-Au couple is presented and similar data for a "flip-chip" mounted Au-refractory gate device is reviewed. The failure mechanisms for both devices are described.

  • Transistors with dual work function metal gates by single full silicid...

  • Abstract: Abstract Metal gate electrodes with two different work functions, ?4.5 and ?4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was ?0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same Toxinv as poly gate.





























 

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