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|Views: (2011) Date: (Publication Date: 24-27 Nov. 2...) Pages: ()|
Abstract: Abstract With multi Gigabit data rates, high speed memory devices run into limitations of the timing margins for data paths on low-cost PCB material. In order to keep system cost low, training mechanisms adapt the timing of two link partners. These mechanisms often represent a challenge for ATE-based test of such devices since the ATE has to have the versatility to adapt to the training mechanisms used by various device types. One of the next high speed memory standards that uses a sophisticated training methodology is GDDR5. In this paper the test challenges of GDDR5 training on ATE are discussed and solutions addressing these challenges are presented. GDDR5 is a specification proposal which is under consideration at the committee level of JEDEC and is a work in progress. At the time of the writing and presentation of this paper a final standard for the GDDR5 specification has not been adopted as a JEDEC final standard.