Split gates: A low swing technique for reducing power for high fanout gates

Abstract:  Abstract We consider the problem of reducing power for heavily loaded intra-module interconnect. Such lines are dominated by a heavy capacitive load with line resistance being smaller than the driver resistance. A method - split gates - of modifying the standard CMOS inverter is provided by splitting the inverter into a driver and receiver circuitry. The scheme allows a reduction in active power by limiting the voltage swing on the interconnect and a reduction in standby power by leveraging the presence of stacked devices. It is a low overhead method which does not require the use of multiple supply voltages and can be incorporated within simple leaf-cells. Simulation results in a MOSIS 0.25µm process are presented for capacitive lines and show a 40% improvement in driver active power, and a 5× improvement in standby leakage. Overall power savings by using the technique in multiplier and multiplicand drivers of 32 × 32 carry-save array multiplier is around 13.2% which is close to the maximum possible 16% gain.