Optimum redundancy design for new-generation EPROMs based on yieldanalysis of previous generation


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      		Views: (2009)   Date: (Publication Date: 7-9 Apr 1992)   Pages: ()

    • Author:  Imamiya  K. Miyamoto  J. Ohtuska  N. Tomita  N. Iyama  Y. Semicond. Device Eng. Lab.  Toshiba Corp.  Kawasaki;  

    • Abstract:  Abstract Failure modes of 4 Mbit EPROMs have been analyzed, and the model to formulate them is proposed. The redundancy scheme of a 16 Mbit EPROM was optimized by the model in consideration of area penalty. In applying the 4 Mbit data to 16 Mbit EPROM, fabrication line improvement was taken into account. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction. The 16 Mbit EPROM has 2 rows×8 blocks redundancy, and the redundancy gives the highest yield in the time when the mass production begins

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