Optimal allocation of multiport memories in datapath synthesis

Abstract:  Abstract In order to optimally allocate multiport memories in datapath synthesis, registers are simultaneously assigned to a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provides a more compact assignment, allowing even fewer ports and fewer module interconnections. The LP model is extended, and a fast heuristic approach that searches for an allocation is presented. This allocation algorithm is part of a more general design tool that generates alternative multiport memory configurations and allows their rapid exploration. The designer specifies a range of design parameters, and can control the thoroughness of the search. Within the limits set by the designer, the program finds the minimum cost configuration having a feasible register allocation. The components of this system are described, and some examples of its use are presented